V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration

We describe V–SAT, a tool for performing design space exploration of System-On-Chip (SOC) architectures. The key components of V–SAT include EXPRESSION, a language for specification of the architecture, SIMPRESS, a simulator generator for analysis/evaluation of the architecture, and the V– SAT GUI front-end for easy specification and detailed analysis. We give a brief overview of the components (EXPRESSION, SIMPRESS and GUI) and, using an example DLX architecture, demonstrate V–SAT’s usefulness in exploration for an embedded SOC codesign flow by specifying and evaluating several modifications to the pipeline structure of the processor. We believe that V–SAT provides a powerful environment, both for early design space exploration, as well as for the detailed design of SOC architectures.